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| ZL30111 POTS Line Card PLL Data Sheet Features * * * * * * * * * Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz Provides 2 styles of 8 kHz framing pulses Automatic entry and exit from freerun mode on reference fail Provides DPLL lock and reference fail indication DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference Less than 0.6 nspp intrinsic jitter on all output clocks 20 MHz external master clock source: clock oscillator or crystal Simple hardware control interface Ordering Information ZL30111QDG ZL30111QDG1 64 Pin TQFP Trays, Bake & Drypack 64 Pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40C to +85C January 2007 Applications * * Synchronizer for POTS line cards Rate convert NTR 8kHz or GPON physical interface clock to TDM clock Description The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. REF_FAIL LOCK REF DPLL Reference Monitor Mode Control C2o C4 C8 F4 F8 RST OSCi OSCo State Machine Master Clock Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved. ZL30111 Table of Contents Data Sheet 1.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 DPLL Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 Zarlink Semiconductor Inc. ZL30111 List of Figures Data Sheet Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - DPLL Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 - Output Timing Referenced to F8o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Zarlink Semiconductor Inc. ZL30111 1.0 1.1 Data Sheet Physical Description Pin Connections F4/F65o IC AGND IC IC NC REF0 NC IC NC IC IC VDD NC IC IC F8/F32o IC C2o AVDD AVDD C8/C32o C4/C65o AGND AGND NC NC AVDD AVDD AVCORE AGND AGND 48 50 30 52 28 54 56 58 22 60 20 62 18 64 2 4 6 8 10 12 14 16 26 24 46 44 42 40 38 36 34 32 ZL30111 IC NC NC AVDD IC IC IC VDD NC GND IC OSCi OSCo RST IC IC Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30111 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30111 does not use the e-Pad TQFP. GND VCORE LOCK REF_FAIL IC IC IC IC IC IC IC VCORE GND AVCORE IC IC 4 Zarlink Semiconductor Inc. ZL30111 1.2 Pin Description Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name GND VCORE LOCK REF_FAIL IC IC IC IC IC IC IC VCORE GND AVCORE IC IC IC IC RST Ground. 0 V. Positive Supply Voltage. +1.8 VDC nominal. Description Data Sheet Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected input reference. Reference Failure Indicator (Output). A logic high at this pin indicates that the REF reference frequency is exhibiting abrupt phase or frequency changes. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Connect to GND. Internal Connection. Connect to GND. Positive Supply Voltage. +1.8 VDC nominal. Ground. 0 V. Positive Analog Supply Voltage. +1.8 VDC nominal. Internal Connection. Leave unconnected. Internal Connection. Connect to VDD. Internal Connection. Connect to GND. Internal Connection. Connect to GND. Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be forced into high impedance. Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. Internal Connection. Leave unconnected. Ground. 0 V. No internal bonding Connection. Leave unconnected. Positive Supply Voltage. +3.3 VDC nominal. Internal Connection. Connect this pin to GND. 20 OSCo 21 OSCi 22 23 24 25 26 IC GND NC VDD IC 5 Zarlink Semiconductor Inc. ZL30111 Pin Description (continued) Pin # 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Name IC IC AVDD NC NC IC AGND AGND AVCORE AVDD AVDD NC NC AGND AGND C4 C8 AVDD AVDD C2o Description Internal Connection. Connect this pin to GND. Internal Connection. Connect this pin to GND. Positive Analog Supply Voltage. +3.3 VDC nominal. No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Internal Connection. Leave unconnected. Analog Ground. 0 V Analog Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal. Positive Analog Supply Voltage. +3.3 VDC nominal. Positive Analog Supply Voltage. +3.3 VDC nominal. No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Analog Ground. 0 V Analog Ground. 0 V Data Sheet Clock 4.096 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbps or 4.096 Mbps. Clock 8.192 MHz (Output). This output is used for ST-BUS and GCI operation at 8.192 Mbps. Positive Analog Supply Voltage. +3.3 VDC nominal. Positive Analog Supply Voltage. +3.3 VDC nominal. Clock 2.048 MHz (Output). This output is used for standard E1 interface timing. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 47 48 IC F8 Internal Connection. Leave unconnected. Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 49 F4 Frame Pulse ST-BUS 2.048 Mbps (Output). This output is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048 Mbps and 4.096 Mbps. Internal Connection. Leave unconnected. Analog Ground. 0 V 50 51 IC AGND 6 Zarlink Semiconductor Inc. ZL30111 Pin Description (continued) Pin # 52 53 54 55 Name IC IC NC REF Description Internal Connection. Connect this pin to GND. Internal Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Data Sheet Reference (Input). This is the input reference sources used for synchronization. One of four possible frequencies may be used: 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz. This pin is internally pulled down to GND. No internal bonding Connection. Leave unconnected. Internal Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Internal Connection. Connect this pin to GND. Internal Connection. Connect this pin to VDD. Positive Supply Voltage. +3.3 VDC nominal. No internal bonding Connection. Leave unconnected. Internal Connection. Connect this pin to GND. Internal Connection. Connect this pin to VDD. 56 57 58 59 60 61 62 63 64 NC IC NC IC IC VDD NC IC IC 7 Zarlink Semiconductor Inc. ZL30111 2.0 Functional Description Data Sheet The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. Figure 1 is a functional block diagram which is described in the following sections. 2.1 Reference Monitor The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. * Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. * * Reference Frequency Detector REF Coarse Frequency Monitor REF_FAIL OR Single Cycle Monitor Mode select state machine DPLL in FreeRun Mode Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into FreeRun mode. 8 Zarlink Semiconductor Inc. ZL30111 2.2 Digital Phase Lock Loop (DPLL) Data Sheet The DPLL of the ZL30111 consists of a phase detector, a loop filter and a digitally controlled oscillator. Phase Detector - the phase detector compares the input reference signal to the feedback signal and provides an error signal corresponding to the phase difference between the two. Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 922 Hz. For stability reasons, the loop filter bandwidth for an 8 kHz reference is limited to a maximum of 58 Hz. Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30111. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lockwindow for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into FreeRun mode, the LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in FreeRun mode, the LOCK pin will go low. In Freerun mode the LOCK pin will go low immediately. 2.3 Frequency Synthesizers The output of the DCO is used by the frequency synthesizer to generate the output clock which is synchronized to the inputs (REF). The frequency synthesizer uses digital techniques to generate output clock and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads. 2.4 State Machine As shown in Figure 1, the state machine controls the DPLL. 2.5 Master Clock The ZL30111 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 9 Zarlink Semiconductor Inc. ZL30111 3.0 DPLL Modes of Operation Data Sheet The ZL30111 has two possible modes of operation; Normal, and Freerun. The ZL30111 starts up in Freerun mode, it automatically transitions to Normal mode if a valid reference is available and transitions to Freerun mode if the reference fails. 3.1 Freerun Mode Freerun mode is typically used when an independent clock source is required or immediately following system power-up before synchronization is achieved. In Freerun mode, the ZL30111 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32 ppm output clock is required, the master clock must also be 32 ppm. See Applications - Section 5.2, "Master Clock". Freerun Mode is also used for short durations while system synchronization is temporarily disrupted. The accuracy of the output clock during these input reference disruptions is better than the accuracy of the master clock (OSCi), but it is off compared to the reference before disruptions. 3.2 Normal Mode Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal mode, the ZL30111 provides timing synchronization signals, which are synchronized to the input (REF). The input reference signal may have a nominal frequency of 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. When the ZL30111 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy of its freerunning local oscillator (see Figure 4). If the ZL30111 determines that its selected reference is disrupted (see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted. If the ZL30111 determines that the reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover from Freerun and transition to Normal mode. When the ZL30111 is operating in Normal mode, if it determines that the input reference is disrupted (Figure 3) then its state machine will cause it to automatically go to Freerun mode. When the ZL30111 determines that its selected reference is not disrupted then the state machine will cause the DPLL to recover from Freerun and transition to Normal mode. REF_FAIL=0 RST Freerun REF_FAIL=1 Normal Figure 4 - DPLL Mode Switching 10 Zarlink Semiconductor Inc. ZL30111 4.0 Measures of Performance Data Sheet The following are some PLL performance indicators and their corresponding definitions. 4.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 4.2 Jitter Generation (Intrinsic Jitter) Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually measured with various band limiting filters depending on the applicable standards. 4.3 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. 4.4 Lock Time This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: * * * initial input to output phase difference initial input to output frequency difference PLL loop filter bandwidth The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. 11 Zarlink Semiconductor Inc. ZL30111 5.0 Applications Data Sheet This section contains ZL30111 application specific details for power supply decoupling, reset operation, clock and crystal operation. 5.1 Power Supply Decoupling Jitter levels on the ZL30111 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30111 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178. 5.2 Master Clock The ZL30111 can use either a clock or crystal as the master timing source. 5.2.1 Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30111, and the OSCo output should be left open as shown in Figure 5. 1 2 3 4 Frequency Tolerance Rise & fall time Duty cycle 20 MHz as required (better than +/-50ppm) < 8 ns 40% to 60% Table 1 - Clock Oscillator Specification ZL30111 OSCi +3.3 V +3.3 V 20 MHz OUT GND 0.1 F OSCo No Connection Figure 5 - Clock Oscillator Circuit 12 Zarlink Semiconductor Inc. ZL30111 5.2.2 Crystal Oscillator Data Sheet Alternatively, a Crystal Oscillator may be used. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. A typical crystal oscillator specification is shown in Table 2. . 1 2 3 4 5 6 Frequency Tolerance Oscillation mode Resonance mode Load capacitance Maximum series resistance 20 MHz as required (better than +/-50ppm) fundamental parallel as required 50 Table 2 - Crystal Oscillator Specification 13 Zarlink Semiconductor Inc. ZL30111 5.3 Power Up Sequence Data Sheet The ZL30111 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of protection diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1.8 V supply (e.g., by using a schottky diode or controlled slew rate) 5.4 Reset Circuit A simple power up reset circuit with about a 60 s reset low time is shown in Figure 6. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30111 +3.3 V R 10 k RST RP 1 k C 10 nF Figure 6 - Power-Up Reset Circuit 14 Zarlink Semiconductor Inc. ZL30111 6.0 6.1 Data Sheet Characteristics AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 8 Supply voltage Core supply voltage Voltage on any digital pin Voltage on OSCi and OSCo pin Current on any pin Storage temperature TQFP 64 pin package power dissipation ESD rating Symbol VDD_R VCORE_R VPIN VOSC IPIN TST PPD VESD -55 Min. -0.5 -0.5 -0.5 -0.3 Max. 4.6 2.5 6 VDD + 0.3 30 125 500 2 Units V V V V mA C mW kV * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 2 3 4 Supply voltage Core supply voltage Operating temperature Input Voltage Sym. VDD VCORE TA VI Min. 3.1 1.7 -40 0 Typ. 3.30 1.80 25 3.3 Max. 3.5 1.9 85 3.5 Units V V C V * Voltages are with respect to ground (GND) unless otherwise stated. 15 Zarlink Semiconductor Inc. ZL30111 DC Electrical Characteristics* Characteristics 1 2 4 5 6 7 8 9 Supply current with: OSCi = 0 V OSCi = Clock, OUT_SEL=0 Core supply current with: OSCi = 0 V OSCi = Clock Schmitt trigger Low to High threshold point Schmitt trigger High to Low threshold point Input leakage current High-level output voltage Sym. IDDS IDD ICORES ICORE Vt+ VtIIL VOH Min. 3.0 32 0 14 1.43 0.80 -105 2.4 Max. 6.5 47 22 20 1.85 1.10 105 Units mA mA A mA V V A V Data Sheet Notes outputs loaded with 30 pF All device inputs are Schmitt trigger type. VI = VDD or 0 V IOH = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs IOL = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs 10 Low-level output voltage VOL 0.4 V * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 7) Characteristics 1 2 3 Threshold voltage Rise and fall threshold voltage high Rise and fall threshold voltage low Sym. VT VHM VLM CMOS 0.5xVDD 0.7xVDD 0.3xVDD Units V V V Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. Timing Reference Points ALL SIGNALS tIF, tOF tIR, tOR V HM VT V LM Figure 7 - Timing Parameter Measurement Voltage Levels 16 Zarlink Semiconductor Inc. ZL30111 AC Electrical Characteristics* - Input Timing (see Figure 8) Characteristics 1 2 3 4 5 8 kHz reference period 2.048 MHz reference period 8.192 MHz reference period 19.44 MHz reference period reference pulse width high or low Symbol tREF8KP tREF2P tREF8P tREF16P tREFW Min. 121 263 63 38 15 Typ. 125 488 122 51 Data Sheet Max. 128 712 175 75 Units s ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-ofRange limits. AC Electrical Characteristics* - Input to Output Timing (see Figure 8) Characteristics 1 2 3 4 5 6 8 kHz reference input to F8o delay 2.048 MHz reference input to C2o delay 2.048 MHz reference input to F8o delay 8.192 MHz reference input to C8o delay 8.192 MHz reference input to F8o delay 19.44 MHz reference input to F8o delay Symbol tREF8KD tREF2D tREF2_F8D tREF8D tREF8_F8D tREF9D_F8D Min. 0 2 2 5 5 0 Max. 8 10 10 13 13 8 Units ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. tREF REF output clock with the same frequency as REF tREF tREF8kD, tREF F8o Figure 8 - Input to Output Timing 17 Zarlink Semiconductor Inc. ZL30111 AC Electrical Characteristics* - Output Timing (see Figure 9) Characteristics 1 2 3 4 5 6 7 8 9 10 11 C2o pulse width low C2o delay F4o pulse width low F4o delay C4o pulse width low C4o delay F8o pulse width high C8o pulse width low C8o delay Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC2L tC2D tF4L tF4D tC4L tC4D tF8H tC8L tC8D tOR tOF Min. 243 -1.0 243 121 121 -1.0 121 60 -1.0 1.0 1.0 Max. 245 1.0 245 123 123 1.0 124 62 1.0 2.0 2.5 Units ns ns ns ns ns ns ns ns ns ns ns Data Sheet Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions and 30 pF load. tF8H F8o tC2L tC2D C2o tF4D tF4L F4o tC4L tC4D C4o tC8L tC8D C8o Figure 9 - Output Timing Referenced to F8o 18 Zarlink Semiconductor Inc. ZL30111 6.2 Performance Characteristics Data Sheet Performance Characteristics* - Functional Characteristics 1 DPLL capture range Min. -130 Typ. Max. +130 Units ppm Notes The 20 MHz Master Clock oscillator set at 0.ppm input reference = 8 kHz, 100 ppm frequency offset input reference 8 kHz, 100 ppm frequency offset Lock Time 2 DPLL 58 Hz Filter 1 s 3 DPLL 922 Hz Filter 1 s * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics* - Unfiltered Intrinsic Jitter Characteristics 1 2 3 4 5 C2o (2.048 MHz) C4o (4.096 MHz) C8o (8.192 MHz) F4o (8 kHz) F8o (8 kHz) Max. [nspp] 0.6 0.6 0.6 0.6 0.6 Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions. 19 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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